Current and future generations of metal-oxide-semiconductor field-effect transistors (MOSFETs) require tight control of parasitic capacitance while simultaneously optimizing metal-semiconductor contact resistance. In FinFET structures, maximizing the contact area can be achieved by creating a contact that wraps around the fin or by growing faceted epitaxial contacts, and then wrapping metal around the faceted epitaxial contact. The adoption of ultra-thin transistor body structures such as FinFET and fully depleted silicon-on-insulator (FDSOI) has exacerbated the problem for logic manufacturing. In order to reduce contact resistance in FinFET structures, device makers are contemplating WAC structures that allow metal-semiconductor contacts with increased area.